HD6432351 Datasheet, PDF (184/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.5.8 Wait Control
There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and
pin wait insertion using the WAIT pin.
Program Wait Insertion
When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to
3 wait states can be inserted automatically between the T_c1 state and T_c2 state, according to the
settings of WCRH and WCRL.
Pin Wait Insertion
When the WAITE bit in BCRH is set to 1, wait input by means of the WAIT pin is enabled
regardless of the setting of the AST bit in ASTCR. When DRAM space is accessed in this state, a
program wait is first inserted. If the WAIT pin is low at the falling edge of ø in the last T_c1 or T_w
state, another T_w state is inserted. If the WAIT pin is held low, T_w states are inserted until it goes
high.
Figure 6-17 shows an example of wait state insertion timing.
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