HD6432351 Datasheet, PDF (710/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

21.3.3 Bus Timing
Table 21-6 lists the bus timing.
Table 21-6 Bus Timing
Condition A: V_CC = 2.7 to 5.5 V, AV_CC = 2.7 to 5.5 V, V_ref = 2.7 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 10 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø= 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
Address delay time
Address setup time
Symbol
t _AD
t _AS
Address hold time
t _AH
Precharge time
t _PCH
CS delay time 1
CS delay time 2
AS delay time
RD delay time 1
RD delay time 2
CAS delay time
Read data setup time
Read data hold time
Read data access
time1
t _CSD1
t _CSD2
t _ASD
t _RSD1
t _RSD2
t _CASD
t _RDS
t _RDH
t _ACC1
Read data access
time2
t _ACC2
Read data access
time3
t _ACC3
Condition A
Condition B
Min Max Min Max Unit
—
40
—
20
ns
0.5 × —
0.5 × —
ns
t _cyc – 30
t _cyc – 15
0.5 × —
0.5 × —
ns
t _cyc – 20
t _cyc – 10
1.5 × —
1.5 × —
ns
t _cyc – 40
t _cyc – 20
—
40
—
20
ns
—
40
—
20
ns
—
40
—
20
ns
—
40
—
20
ns
—
40
—
20
ns
—
40
—
20
ns
30
—
15
—
ns
0
—
0
—
ns
—
1.0 × —
1.0 × ns
t _cyc – 50
t _cyc – 25
—
1.5 × —
1.5 × ns
t _cyc – 50
t _cyc – 25
—
2.0 × —
2.0 × ns
t _cyc – 50
t _cyc – 25
Test Conditions
Figure 21-8 to
Figure 21-15
690