HD6432351 Datasheet, PDF (553/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

13.1.4 Register Configuration
The SCI has the internal registers shown in table 13-2. These registers are used to specify
asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control
transmitter/receiver.
Table 13-2 SCI Registers
Channel Name
Abbreviation
0
Serial mode register 0
SMR0
Bit rate register 0
BRR0
Serial control register 0 SCR0
Transmit data register 0 TDR0
Serial status register 0
SSR0
Receive data register 0 RDR0
Smart card mode register 0 SCMR0
1
Serial mode register 1
SMR1
Bit rate register 1
BRR1
Serial control register 1 SCR1
Transmit data register 1 TDR1
Serial status register 1
SSR1
Receive data register 1 RDR1
Smart card mode register 1 SCMR1
All
Module stop control register MSTPCR
Notes: 1. Lower 16 bits of the address.
2. Can only be written with 0 for flag clearing.
R/W
R/W
R/W
R/W
R/W
R/(W)*²
R
R/W
R/W
R/W
R/W
R/W
R/(W)*²
R
R/W
R/W
Initial Value
H'00
H'FF
H'00
H'FF
H'84
H'00
H'F2
H'00
H'FF
H'00
H'FF
H'84
H'00
H'F2
H'3FFF
Address*¹
H'FF78
H'FF79
H'FF7A
H'FF7B
H'FF7C
H'FF7D
H'FF7E
H'FF80
H'FF81
H'FF82
H'FF83
H'FF84
H'FF85
H'FF86
H'FF3C
533