HD6432351 Datasheet, PDF (580/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 13-10 Serial Transfer Formats (Asynchronous Mode)
CHR
SMR Settings
PE MP STOP
Serial Transfer Format and Frame Length
1 2 3 4 5 6 7 8 9 10 11 12
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P STOP
1
1
0
1
S
7-bit data
P STOP STOP
0
—
1
0
S
8-bit data
MPB STOP
0
—
1
1
S
8-bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
Legend
S
: Start bit
STOP : Stop bit
P
: Parity bit
MPB : Multiprocessor bit
7-bit data
MPB STOP STOP
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