HD6432351 Datasheet, PDF (340/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

9.2.2 Register Configuration
Table 9-2 shows the port 1 register configuration.
Table 9-2 Port 1 Registers
Name
Abbreviation
R/W
Port 1 data direction register
P1DDR
W
Port 1 data register
P1DR
R/W
Port 1 register
PORT1
R
Note: * Lower 16 bits of the address.
Initial Value
H'00
H'00
Undefined
Address*
H'FEB0
H'FF60
H'FF50
Port 1 Data Direction Register (P1DDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read.
Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P1DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. As the PPG, TPU, and DMAC are
initialized by a manual reset, the pin states are determined by the P1DDR and P1DR
specifications.
Port 1 Data Register (P1DR)
Bit
:
Initial value :
R/W
:
7
P17DR
0
R/W
6
P16DR
0
R/W
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
0
P10DR
0
R/W
P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P1₇ to P1₀).
P1DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
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