HD6432351 Datasheet, PDF (381/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Modes 4 and 5: In modes 4 and 5, the lower 5 bits of port A are designated as address outputs
automatically, while the upper 3 bits function as address outputs or input ports and interrupt input
pins. Input or output can be specified individually for the upper 3 bits. Setting one of bits
PA7DDR to PA5DDR to 1 makes the corresponding port A pin an address output, while clearing
the bit to 0 makes the pin an input port.
Port A pin functions in modes 4 and 5 are shown in figure 9-9.
Port A
When PADDR = 1
A₂₃ (output)
A₂₂ (output)
A₂₁ (output)
A₂₀ (output)
A₁₉ (output)
A₁₈ (output)
A₁₇ (output)
A₁₆ (output)
When PADDR = 0
PA₇ (input)/IRQ7 (input)
PA₆ (input)/IRQ6 (input)
PA₅ (input)/IRQ5 (input)
A₂₀ (output)
A₁₉ (output)
A₁₈ (output)
A₁₇ (output)
A₁₆ (output)
Figure 9-9 Port A Pin Functions (Modes 4 and 5)
Mode 6 [H8S/2351 Only]: In mode 6, port A pins function as address outputs or input ports and
interrupt input pins. Input or output can be specified on an individual bit basis. Setting a PADDR
bit to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes
the pin an input port.
Port A pin functions in mode 6 are shown in figure 9-10.
Port A
When PADDR = 1
A₂₃ (output)
A₂₂ (output)
A₂₁ (output)
A₂₀ (output)
A₁₉ (output)
A₁₈ (output)
A₁₇ (output)
A₁₆ (output)
When PADDR = 0
PA₇ (input)/IRQ7 (input)
PA₆ (input)/IRQ6 (input)
PA₅ (input)/IRQ5 (input)
PA₄ (input)/IRQ4 (input)
PA₃ (input)
PA₂ (input)
PA₁ (input)
PA₀ (input)
Figure 9-10 Port A Pin Functions (Mode 6)
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