HD6432351 Datasheet, PDF (724/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

21.3.5 Timing of On-Chip Supporting Modules
Table 21-8 lists the timing of on-chip supporting modules.
Table 21-8 Timing of On-Chip Supporting Modules
Condition A: V_CC = 2.7 V to 5.5 V, AV_CC = 2.7 V to 5.5 V, V_ref = 2.7 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 10 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
PORT
PPG
TPU
Condition A
Symbol Min Max
Output data delay t _PWD
time
— 100
Input data setup t _PRS
time
50 —
Input data hold
t _PRH
time
50 —
Pulse output delay t _POD
time
— 100
Timer output delay t _TOCD
time
— 100
Timer input setup t _TICS
time
50 —
Timer clock input t _TCKS
setup time
50 —
Timer
clock
pulse
width
Single
edge
Both
edges
t _TCKWH
t _TCKWL
1.5 —
2.5 —
Condition B
Min Max
— 50
30 —
30 —
— 50
— 50
30 —
30 —
1.5 —
2.5 —
Unit Test Conditions
ns Figure 21-22
ns Figure 21-23
ns Figure 21-24
ns Figure 21-25
t _cyc
704