HD6432351 Datasheet, PDF (455/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

10.2.8 Timer Start Register (TSTR)
Bit
:
7
—
Initial value :
0
R/W
:
—
6
5
4
3
2
1
0
—
CST5 CST4 CST3 CST2 CST1 CST0
0
0
0
0
0
0
0
—
R/W R/W R/W R/W R/W R/W
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5.
TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating
mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Bits 7 and 6—Reserved: Should always be written with 0.
Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for
TCNT.
Bit n
CSTn
Description
0
TCNTn count operation is stopped
(Initial value)
1
TCNTn performs count operation
Note:
n = 5 to 0
If 0 is written to the CST bit during operation with the TIOC pin designated for output, the
counter stops but the TIOC pin output compare output level is retained. If TIOR is written to
when the CST bit is cleared to 0, the pin output level will be changed to the set initial output
value.
435