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HD6432351 Datasheet, PDF (715/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise
ø
A23 to A0
CS5 to CS2
(RAS)
CAS
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
Tp
Tr
TC1
TC2
tAD
tAD
tAS
tAH
tPCH
tACC4
tCSD2
tCASD
tACC1
tCSD1
tCASD
tACC3
tRDS tRDH
tWRD1
tWRD1
tWCS
tWDD tWDS
tWCH
tWDH
Figure 21-11 DRAM Bus Timing
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