HD6432351 Datasheet, PDF (39/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 1-3 Pin Functions (cont)
Type
I/O ports
Symbol
P6₇ to
P6₀
PA₇ to
PA₀
Pin No.
TFP-120 FP-128 I/O
29 to 32, 33, 34, I/O
63 to 60 37, 38,
71 to 69,
66
28 to 25, 32 to 29, I/O
23 to 20 27 to 24
PB₇ to
PB₀
19 to 16, 23 to 20, I/O
14 to 11 18 to 15
PC₇ to
PC₀
10 to 7, 14 to 11, I/O
5 to 2 9 to 6
PD₇ to
PD₀
51 to 48, 57 to 54, I/O
46 to 43 52 to 49
PE₇ to
PE₀
42 to 39, 48 to 45, I/O
37 to 34 43 to 40
PF₇ to
PF₀
80,
88,
I/O
82 to 88 90 to 96
PG₄ to
PG₀
120 to 2, 1,
I/O
116
128 to
126
Note: * Only applies to the H8S/2351.
Name and Function
Port 6: An 8-bit I/O port. Input or
output can be designated for each bit
by means of the port 6 data direction
register (P6DDR).
Port A: An 8-bit I/O port. Input or
output can be designated for each bit
by means of the port A data direction
register (PADDR).
Port B*: An 8-bit I/O port. Input or
output can be designated for each bit
by means of the port B data direction
register (PBDDR).
Port C*: An 8-bit I/O port. Input or
output can be designated for each bit
by means of the port C data direction
register (PCDDR).
Port D*: An 8-bit I/O port. Input or
output can be designated for each bit
by means of the port D data direction
register (PDDDR).
Port E: An 8-bit I/O port. Input or
output can be designated for each bit
by means of the port E data direction
register (PEDDR).
Port F: An 8-bit I/O port. Input or
output can be designated for each bit
by means of the port F data direction
register (PFDDR).
Port G: A 5-bit I/O port. Input or
output can be designated for each bit
by means of the port G data direction
register (PGDDR).
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