HD6432351 Datasheet, PDF (497/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 10-46
shows the timing for status flag clearing by the CPU, and figure 10-47 shows the timing for status
flag clearing by the DTC or DMAC.
ø
Address
Write signal
Status flag
Interrupt
request
signal
TSR write cycle
T1
T2
TSR address
Figure 10-46 Timing for Status Flag Clearing by CPU
ø
Address
Status flag
Interrupt
request
signal
DTC/DMAC
read cycle
T1
T2
DTC/DMAC
write cycle
T1
T2
Source address
Destination
address
Figure 10-47 Timing for Status Flag Clearing by DTC/DMAC Activation
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