HD6432351 Datasheet, PDF (318/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs (cont)
Interrupt Source
Origin of
Interrupt
Source
Vector Vector
Number Address DTCE*
Priority
TGI3A (GR3A compare match/ TPU
48
input capture)
channel 3
H'0460 DTCEC5 High
TGI3B (GR3B compare match/
input capture)
49
H'0462 DTCEC4
TGI3C (GR3C compare match/
input capture)
50
H'0464 DTCEC3
TGI3D (GR3D compare match/
input capture)
51
H'0466 DTCEC2
TGI4A (GR4A compare match/ TPU
56
input capture)
channel 4
H'0470 DTCEC1
TGI4B (GR4B compare match/
input capture)
57
H'0472 DTCEC0
TGI5A (GR5A compare match/ TPU
60
input capture)
channel 5
H'0478 DTCED5
TGI5B (GR5B compare match/
input capture)
61
H'047A DTCED4
DMTEND0A (DMAC transfer end 0) DMAC
72
H'0490 DTCEE7
DMTEND0B (DMAC transfer end 1)
73
H'0492 DTCEE6
DMTEND1A (DMAC transfer end 2)
74
H'0494 DTCEE5
DMTEND1B (DMAC transfer end 3)
75
H'0496 DTCEE4
RXI0 (reception complete 0)
SCI
81
TXI0 (transmit data empty 0)
channel 0
82
H'04A2
H'04A4
DTCEE3
DTCEE2
RXI1 (reception complete 1)
SCI
85
TXI1 (transmit data empty 1)
channel 1
86
H'04AA
H'04AC
DTCEE1
DTCEE0 Low
Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
298