HD6432351 Datasheet, PDF (474/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Examples of Cascaded Operation: Figure 10-22 illustrates the operation when counting upon
TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated
as input capture registers, and TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
TCNT1
clock
TCNT1
TCNT2
clock
H'03A1
TCNT2
H'FFFF
TIOCA1,
TIOCA2
TGR1A
H'03A2
H'0000
H'03A2
H'0001
TGR2A
H'0000
Figure 10-22 Example of Cascaded Operation (1)
Figure 10-23 illustrates the operation when counting upon TCNT2 overflow/underflow has been
set for TCNT1, and phase counting mode has been designated for channel 2.
TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow.
TCLKA
TCLKB
TCNT2
TCNT1
FFFD FFFE FFFF 0000 0001
0002
0001 0000 FFFF
0000
0001
0000
Figure 10-23 Example of Cascaded Operation (2)
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