HD6432351 Datasheet, PDF (258/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Figure 7-7 illustrates operation in repeat mode.
Address T
Transfer
1 byte or word transfer performed in
response to 1 transfer request
IOAR
Address B
Legend
Address T = L
Address B = L + (–1)^DTID • (2^DTSZ • (N–1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 7-7 Operation in Repeat mode
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can be set for channel B only.
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