HD6432351 Datasheet, PDF (123/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont)
Interrupt Source
Origin of
Vector Address*
Interrupt Vector Normal Advanced
Source Number Mode Mode
IPR
Reserved
—
64
H'0080 H'0100
65
H'0082 H'0104
66
H'0084 H'0108
67
H'0086 H'010C
68
H'0088 H'0110
69
H'008A H'0114
70
H'008C H'0118
71
H'008E H'011C
DEND0A (channel 0/
DMAC 72
channel 0A transfer end)
H'0090 H'0120
IPRJ6 to 4
DEND0B (channel 0B
transfer end)
73
H'0092 H'0124
DEND1A (channel 1/
channel 1A transfer end)
74
H'0094 H'0128
DEND1B (channel 1B
transfer end)
75
H'0096 H'012C
Reserved
—
76
77
78
79
ERI0 (receive error 0)
SCI
80
RXI0 (reception completed 0) channel 0 81
TXI0 (transmit data empty 0)
82
TEI0 (transmission end 0)
83
H'0098
H'009A
H'009C
H'009E
H'00A0
H'00A2
H'00A4
H'00A6
H'0130
H'0134
H'0138
H'013C
H'0140
H'0144
H'0148
H'014C
IPRJ2 to 0
ERI1 (receive error 1)
SCI
84
RXI1 (reception completed 1) channel 1 85
TXI1 (transmit data empty 1)
86
TEI1 (transmission end 1)
87
H'00A8
H'00AA
H'00AC
H'00AE
H'0150
H'0154
H'0158
H'015C
IPRK6 to 4
Reserved
—
88
H'00B0 H'0160
IPRK2 to 0
89
H'00B2 H'0164
90
H'00B4 H'0168
91
H'00B6 H'016C
Note: * Lower 16 bits of the start address.
Priority
High
Low
103