HD6432351 Datasheet, PDF (842/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

WCRH—Wait Control Register H
H'FED2
Bus Controller
Bit
:
Initial value :
Read/Write :
7
W71
1
R/W
6
W70
1
R/W
5
W61
1
R/W
4
W60
1
R/W
3
W51
1
R/W
2
W50
1
R/W
1
W41
1
R/W
0
W40
1
R/W
Area 4 Wait Control
0 0 Program wait not inserted
1 1 program wait state inserted
1 0 2 program wait states inserted
1 3 program wait states inserted
Area 5 Wait Control
0 0 Program wait not inserted
1 1 program wait state inserted
1 0 2 program wait states inserted
1 3 program wait states inserted
Area 6 Wait Control
0 0 Program wait not inserted
1 1 program wait state inserted
1 0 2 program wait states inserted
1 3 program wait states inserted
Area 7 Wait Control
0 0 Program wait not inserted
1 1 program wait state inserted
1 0 2 program wait states inserted
1 3 program wait states inserted
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