HD6432351 Datasheet, PDF (537/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

12.1.3 Pin Configuration
Table 12-1 describes the WDT output pin.
Table 12-1 WDT Pin
Name
Watchdog timer overflow
Symbol I/O
WDTOVF Output
Function
Outputs counter overflow signal in watchdog
timer mode
12.1.4 Register Configuration
The WDT has three registers, as summarized in table 12-2. These registers control clock selection,
WDT mode switching, and the reset signal.
Table 12-2 WDT Registers
Address*¹
Name
Abbreviation R/W
Initial Value Write*² Read
Timer control/status register TCSR
R/(W)*³ H'18
H'FFBC H'FFBC
Timer counter
TCNT
R/W H'00
H'FFBC H'FFBD
Reset control/status register RSTCSR
R/(W)*³ H'1F
H'FFBE H'FFBF
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 12.2.4, Notes on Register Access.
3. Only a write of 0 is permitted to bit 7, to clear the flag.
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