HD6432351 Datasheet, PDF (867/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

SBYCR—Standby Control Register
H'FF38
Power-Down State
Bit
:
7
6
5
4
3
2
SSBY STS2 STS1 STS0 OPE
—
Initial value :
0
0
0
0
1
0
Read/Write : R/W
R/W
R/W
R/W
R/W
—
1
0
—
—
0
0
—
R/W
Output Port Enable
Reserved
Only 0 should be written
to this bit
0 In software standby mode, address bus and
bus control signals are high-impedance
1 In software standby mode, address bus and
bus control signals retain output state
Standby Timer Select
0 0 0 Standby time = 8192 states
1 Standby time = 16384 states
1 0 Standby time = 32768 states
1 Standby time = 65536 states
1 0 0 Standby time = 131072 states
1 Standby time = 262144 states
1 0 Reserved
1 Standby time = 16 states
Software Standby
0 Transition to sleep mode after execution of SLEEP instruction
1 Transition to software standby mode after execution of SLEEP instruction
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