HD6432351 Datasheet, PDF (198/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Full access
T₁
T₂
Burst access
T₁
T₁
ø
Address bus
Only lower address changed
CS0
AS
RD
Data bus
Read data Read data Read data
Figure 6-30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)
6.7.3 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait
Control.
Wait states cannot be inserted in a burst cycle.
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