HD6432351 Datasheet, PDF (222/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR
to specify the data transfer direction (source or destination). The function of this bit is therefore
different in dual address mode and single address mode.
DMABCR Bit 4
SAE
DTDIR
0
0
1
1
0
1
Description
Transfer with MAR as source address and IOAR as destination
address
(Initial value)
Transfer with IOAR as source address and MAR as destination address
Transfer with MAR as source address and DACK pin as write strobe
Transfer with DACK pin as read strobe and MAR as destination address
202