HD6432351 Datasheet, PDF (262/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Figure 7-10 shows an example of the setting procedure for single address mode (when sequential
mode is specified).
Single address
mode setting
Set DMABCRH
[1]
Set transfer source and
transfer destination
[2]
addresses
Set number of transfers [3]
Set DMACR
[4]
Read DMABCRL
[5]
Set DMABCRL
[6]
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Set the SAE bit to 1 to select single address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
[2] Set the transfer source address/transfer
destination address in MAR.
[3] Set the number of transfers in ETCR.
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Clear the RPE bit to 0 to select sequential
mode.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set the DTE bit to 1 to enable transfer.
Single address mode
Figure 7-10 Example of Single Address Mode Setting Procedure (When Sequential Mode is
Specified)
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