HD6432351 Datasheet, PDF (544/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

12.3 Operation
12.3.1 Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent
TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows
occurs. This ensures that TCNT does not overflow while the system is operating normally. If
TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF
signal is output. This is shown in figure 12-4. This WDTOVF signal can be used to reset the
system. The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when
RSTE = 0.
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the H8S/2350
Series internally is generated at the same time as the WDTOVF signal. This reset can be selected
as a power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR. The
internal reset signal is output for 518 states.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
TCNT count
H'FF
Overflow
524
H'00
WT/IT=1
TME=1
H'00 written
to TCNT
WDTOVF signal
Internal reset signal*¹
Legend
WT/IT : Timer mode select bit
TME : Timer enable bit
WOVF=1
WDTOVF and
internal reset are
generated
Time
WT/IT=1 H'00 written
TME=1 to TCNT
132 states*²
518 states
Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1.
2. 130 states when the RSTE bit is cleared to 0.
Figure 12-4 Watchdog Timer Operation