HD6432351 Datasheet, PDF (625/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

14.3.4 Register Settings
Table 14-3 shows a bit map of the registers used by the smart card interface.
Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described
below.
Table 14-3 Smart Card Interface Register Settings
Bit
Register Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SMR
GM
0
1
O/E
1
0
CKS1
BRR
BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1
SCR
TIE
RIE
TE
RE
0
0
CKE1*
TDR
TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1
SSR
TDRE RDRF ORER ERS
PER
TEND 0
RDR
RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1
SCMR
—
—
—
—
SDIR SINV —
Notes: — : Unused bit.
*: The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0.
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF
SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in
GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1
if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section
14.3.5, Clock.
BRR Setting: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of
calculating the value to be set.
SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI.
For details, see section 13, Serial Communication Interface.
Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these
bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in
SMR is set to 1, clock output is performed. The clock output can also be fixed high or low.
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