HD6432351 Datasheet, PDF (804/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table A-7 Condition Code Modification (cont)
Instruction
SUB
SUBS
SUBX
TAS
TRAPA
XOR
XORC
HNZ VC
—————
—
0—
—————
—
0—
Definition
H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4
N = Rm
Z = Rm · Rm–1 · ^...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4
N = Rm
Z = Z' · Rm · ^...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
N = Dm
Z = Dm · Dm–1 · ^...... · D0
N = Rm
Z = Rm · Rm–1 · ^...... · R0
Stores the corresponding bits of the result.
No flags change when the operand is EXR.
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