HD6432351 Datasheet, PDF (551/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

13.1.2 Block Diagram
Figure 13-1 shows a block diagram of the SCI.
Module data bus
RxD
TxD
SCK
RDR
RSR
TDR
SCMR
BRR
SSR
TSR
SCR
SMR
Transmission/
reception control
Baud rate
generator
Parity generation
Clock
Parity check
External clock
Legend
SCMR
RSR
RDR
TSR
TDR
SMR
SCR
SSR
BRR
: Smart Card mode register
: Receive shift register
: Receive data register
: Transmit shift register
: Transmit data register
: Serial mode register
: Serial control register
: Serial status register
: Bit rate register
Figure 13-1 Block Diagram of SCI
ø
ø/4
ø/16
ø/64
TEI
TXI
RXI
ERI
Internal
data bus
531