HD6432351 Datasheet, PDF (111/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The H8S/2350 Series controls interrupts by means of an interrupt controller. The interrupt
controller has the following features:
• Two interrupt control modes
 Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in
the system control register (SYSCR).
• Priorities settable with IPR
 An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI.
 NMI is assigned the highest priority level of 8, and can be accepted at all times.
• Independent vector addresses
 All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine.
• Nine external interrupts
 NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling
edge can be selected for NMI.
 Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7
to IRQ0.
• DTC and DMAC control
 DTC and DMAC activation is performed by means of interrupts.
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