HD6432351 Datasheet, PDF (459/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Examples of 8-bit register access operation are shown in figures 10-3, 10-4, and 10-5.
Bus
master
Internal data bus
H
L
Bus interface
Module
data bus
TCR
Figure 10-3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
Internal data bus
H
Bus
master ^L
Bus interface
Module
data bus
TMDR
Figure 10-4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
Internal data bus
H
Bus
master ^L
Bus interface
Module
data bus
TCR
TMDR
Figure 10-5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]
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