HD6432351 Datasheet, PDF (11/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.10.2 Operation .............................................................................................................. 185
6.10.3 Pin States in External Bus Released State ............................................................ 186
6.10.4 Transition Timing ................................................................................................. 187
6.10.5 Usage Note............................................................................................................ 188
6.11 Bus Arbitration................................................................................................................... 188
6.11.1 Overview............................................................................................................... 188
6.11.2 Operation .............................................................................................................. 188
6.11.3 Bus Transfer Timing ............................................................................................. 189
6.11.4 External Bus Release Usage Note ........................................................................ 189
6.12 Resets and the Bus Controller............................................................................................ 190
Section 7 DMA Controller .............................................................................................. 191
7.1 Overview............................................................................................................................ 191
7.1.1 Features ................................................................................................................. 191
7.1.2 Block Diagram...................................................................................................... 192
7.1.3 Overview of Functions.......................................................................................... 193
7.1.4 Pin Configuration.................................................................................................. 195
7.1.5 Register Configuration.......................................................................................... 196
7.2 Register Descriptions (1) (Short Address Mode) .............................................................. 197
7.2.1 Memory Address Registers (MAR)...................................................................... 198
7.2.2 I/O Address Register (IOAR) ............................................................................... 199
7.2.3 Execute Transfer Count Register (ETCR)............................................................ 199
7.2.4 DMA Control Register (DMACR) ....................................................................... 200
7.2.5 DMA Band Control Register (DMABCR) ........................................................... 205
7.3 Register Descriptions (2) (Full Address Mode) ................................................................. 211
7.3.1 Memory Address Register (MAR)........................................................................ 211
7.3.2 I/O Address Register (IOAR) ............................................................................... 211
7.3.3 Execute Transfer Count Register (ETCR)............................................................ 212
7.3.4 DMA Control Register (DMACR) ....................................................................... 213
7.3.5 DMA Band Control Register (DMABCR) ........................................................... 217
7.4 Register Descriptions (3) ................................................................................................... 222
7.4.1 DMA Write Enable Register (DMAWER)........................................................... 222
7.4.2 DMA Terminal Control Register (DMATCR) ..................................................... 225
7.4.3 Module Stop Control Register (MSTPCR)........................................................... 226
7.5 Operation............................................................................................................................ 227
7.5.1 Transfer Modes ..................................................................................................... 227
7.5.2 Sequential Mode ................................................................................................... 230
7.5.3 Idle Mode.............................................................................................................. 233
7.5.4 Repeat Mode ......................................................................................................... 236
7.5.5 Single Address Mode............................................................................................ 240
7.5.6 Normal Mode........................................................................................................ 243
7.5.7 Block Transfer Mode............................................................................................ 246
7.5.8 DMAC Activation Sources ................................................................................... 252
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