HD6432351 Datasheet, PDF (214/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 7-1 (2) Overview of DMAC Functions (Full Address Mode)
Address Register Bit Length
Transfer Mode
Transfer Source
Source
Destination
Normal mode
24
24
• Auto-request
 Transfer request retained
internally
• Auto-request
 Transfers continue for the
specified number of times (1 to
65536)
 Choice of burst or cycle steal
transfer
• External request
• External request
 1-byte or 1-word transfer
executed for one transfer request
 1 to 65536 transfers
Block transfer mode
• TPU channel 0 to 5 ²⁴
24
• Specified block size transfer
executed for one transfer request
compare match/input
capture A interrupt
• 1 to 65536 transfers
• Either source or destination
specifiable as block area
• Block size: 1 to 256 bytes or words
• SCI transmission
complete interrupt
• SCI reception
complete interrupt
• External request
• A/D converter
conversion end
interrupt
194