HD6432351 Datasheet, PDF (801/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table A-7 Condition Code Modification (cont)
Instruction
CMP
DAA
DAS
DEC
DIVXS
DIVXU
EEPMOV
EXTS
EXTU
INC
JMP
JSR
LDC
LDM
LDMAC
MAC
HNZ VC
*
*
*
*
—
—
—
——
—
——
—————
—
0—
—0
—
0—
—
—————
—————
—————
Definition
H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4
N = Rm
Z = Rm · Rm–1 · ^...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
N = Rm
Z = Rm · Rm–1 · ^...... · R0
C: decimal arithmetic carry
N = Rm
Z = Rm · Rm–1 · ^...... · R0
C: decimal arithmetic borrow
N = Rm
Z = Rm · Rm–1 · ^...... · R0
V = Dm · Rm
N = Sm · Dm + Sm · Dm
Z = Sm · Sm–1 · ^...... · S0
N = Sm
Z = Sm · Sm–1 · ^...... · S0
N = Rm
Z = Rm · Rm–1 · ^...... · R0
Z = Rm · Rm–1 · ^...... · R0
N = Rm
Z = Rm · Rm–1 · ^...... · R0
V = Dm · Rm
Stores the corresponding bits of the result.
No flags change when the operand is EXR.
Cannnot be used in the H8S/2350 Series
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