HD6432351 Datasheet, PDF (233/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

ETCRB
Block Transfer Counter
Bit
:
ETCRB :
Initial value :
R/W
:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
* * * * * * * * * * * * * * **
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the
block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when
the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block
size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any
desired number of bytes or words.
ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is
decremented by 1 each time a block is transferred, and transfer ends when the count reaches
H'0000.
7.3.4 DMA Control Register (DMACR)
DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel.
In full address mode, DMACRA and DMACRB have different functions.
DMACR is initialized to H'0000 by a reset, and in standby mode.
DMACRA
Bit
:
15
14
13
12
11
10
9
8
DMACRA : DTSZ SAID SAIDE BLKDIR BLKE
—
—
—
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W R/W
R/W R/W R/W
R/W R/W
DMACRB
Bit
:
7
6
5
4
3
2
1
0
DMACRB :
—
DAID DAIDE
—
DTF3 DTF2 DTF1 DTF0
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W R/W
R/W R/W R/W
R/W R/W
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