|
HD6432351 Datasheet, PDF (805/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
|
◁ |
Appendix B Internal I/O Register
B.1 Addresses
Address Register
(low) Name Bit 7
HâF800
to
HâFBFF
MRA
SAR
SM1
Bit 6
SM0
Bit 5
DM1
Bit 4
DM0
Bit 3
MD1
Bit 2
MD0
Bit 1
DTS
Bit 0
Sz
Module Name
DTC
Data Bus
Width
16/32* bit
MRB CHNE DISEL â
â
â
â
â
â
DAR
CRA
CRB
HâFE80 TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU3
16 bit
HâFE81 TMDR3 â
â
BFB BFA MD3 MD2 MD1 MD0
HâFE82 TIOR3H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
HâFE83 TIOR3L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0
HâFE84 TIER3 TTGE â
â
TCIEV TGIED TGIEC TGIEB TGIEA
HâFE85 TSR3 â
â
â
TCFV TGFD TGFC TGFB TGFA
HâFE86 TCNT3
HâFE87
HâFE88 TGR3A
HâFE89
HâFE8A TGR3B
HâFE8B
HâFE8C TGR3C
HâFE8D
HâFE8E TGR3D
HâFE8F
Note: * Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as
register information, and 16 bits otherwise.
785
|
▷ |