HD6432351 Datasheet, PDF (204/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.9 Write Data Buffer Function
The H8S/2350 Series has a write data buffer function in the external data bus. Using the write data
buffer function enables external writes and DMA single address mode transfers to be executed in
parallel with internal accesses. The write data buffer function is made available by setting the
WDBE bit in BCRL to 1.
Figure 6-36 shows an example of the timing when the write data buffer function is used. When
this function is used, if an external write or DMA single address mode transfer continues for 2
states or longer, and there is an internal access next, only an external write is executed in the first
state, but from the next state onward an internal access (on-chip memory or internal I/O register
read/write) is executed in parallel with the external write rather than waiting until it ends.
On-chip memory read Internal I/O register read
External write cycle
T₁
T₂
T_W
T_W
T₃
Internal address bus
Internal read signal
Internal memory Internal I/O register address
A₂₃ to A₀
External
space
write
CSn
HWR, LWR
External address
D₁₅ to D₀
Figure 6-36 Example of Timing when Write Data Buffer Function is Used
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