HD6432351 Datasheet, PDF (210/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.12 Resets and the Bus Controller
In a power-on reset, the H8S/2350, including the bus controller, enters the reset state at that point,
and an executing bus cycle is discontinued.
In a manual reset, the bus controller’s registers and internal state are maintained, and an executing
external bus cycle is completed. In this case, WAIT input is ignored. Also, since the DMAC is
initialized by a manual reset, DACK and TEND output is disabled and these pins become I/O
ports controlled by DDR and DR.
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