HD6432351 Datasheet, PDF (64/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 2-3 Instructions Classified by Function (cont)
Type
Arithmetic
operations
Instruction
DIVXS
Size*
B/W
CMP
B/W/L
NEG
EXTU
B/W/L
W/L
EXTS
W/L
TAS
B
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Function
Rd ÷ Rs → Rd
Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-
bit remainder.
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another
general register or with immediate data, and sets CCR
bits according to the result.
0 – Rd → Rd
Takes the two's complement (arithmetic complement) of
data in a general register.
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by padding with zeros on the left.
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by extending the sign bit.
@ERd – 0, 1 → (<bit 7> of @Erd)
Tests memory contents, and sets the most significant bit
(bit 7) to 1.
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