HD6432351 Datasheet, PDF (859/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

DMABCRH — DMA Band Control Register
DMABCRL — DMA Band Control Register
H'FF06
H'FF07
DMAC
DMAC
Full address mode
Bit
:
15
14
13
DMABCRH : FAE1 FAE0
—
Initial value :
0
0
0
Read/Write :
R/W
R/W
R/W
12
11
10
9
8
—
DTA1
—
DTA0
—
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Channel 0 Data Transfer Acknowledge
0 Clearing of selected internal interrupt source at time of
DMA transfer is disabled
1 Clearing of selected internal interrupt source at time of
DMA transfer is enabled
Channel 1 Data Transfer Acknowledge
0 Clearing of selected internal interrupt source at time of
DMA transfer is disabled
1 Clearing of selected internal interrupt source at time of
DMA transfer is enabled
Channel 0 Full Address Enable
0 Short address mode
1 Full address mode
Channel 1 Full Address Enable
0 Short address mode
1 Full address mode
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