HD6432351 Datasheet, PDF (170/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.4.4 Basic Timing
8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space.
When an 8-bit access space is accessed, the upper half (D₁₅ to D₈) of the data bus is used.
The LWR pin is fixed high. Wait states cannot be inserted.
Bus cycle
T₁
T₂
ø
Address bus
CSn
AS
RD
Read
D₁₅ to D₈
Valid
D₇ to D₀
Invalid
HWR
Write
LWR
D₁₅ to D₈
D₇ to D₀
Note: n = 0 to 7
High
Valid
High impedance
Figure 6-6 Bus Timing for 8-Bit 2-State Access Space
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