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HD6432351 Datasheet, PDF (802/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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Table A-7 Condition Code Modification (cont)
Instruction
MOV
MOVFPE
MOVTPE
MULXS
MULXU
NEG
NOP
NOT
OR
ORC
POP
PUSH
ROTL
ROTR
HNZ VC
â
0â
â
ââ
âââââ
âââââ
â
0â
â
0â
â
0â
â
0â
â
0
â
0
Definition
N = Rm
Z = Rm · Rmâ1 · ...... · R0
Can not be used in the H8S/2350 Series
N = R2m
Z = R2m · R2mâ1 · ...... · R0
H = Dmâ4 + Rmâ4
N = Rm
Z = Rm · Rmâ1 · ...... · R0
V = Dm · Rm
C = Dm + Rm
N = Rm
Z = Rm · Rmâ1 · ...... · R0
N = Rm
Z = Rm · Rmâ1 · ...... · R0
Stores the corresponding bits of the result.
No flags change when the operand is EXR.
N = Rm
Z = Rm · Rmâ1 · ...... · R0
N = Rm
Z = Rm · Rmâ1 · ...... · R0
N = Rm
Z = Rm · Rmâ1 · ...... · R0
C = Dm (1-bit shift) or C = Dmâ1 (2-bit shift)
N = Rm
Z = Rm · Rmâ1 · ...... · R0
C = D0 (1-bit shift) or C = D1 (2-bit shift)
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