HD6432351 Datasheet, PDF (836/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

P2DDR—Port 2 Data Direction Register
H'FEB1
Port 2
Bit
:
Initial value :
Read/Write :
7
6
5
4
3
2
1
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Specify input or output for individual port 2 pins
P3DDR—Port 3 Data Direction Register
H'FEB2
Port 3
Bit
:
7
6
5
4
3
2
1
0
Initial value :
Read/Write :
—
— P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Undefined Undefined 0
0
0
0
0
0
—
—
W
W
W
W
W
W
Specify input or output for individual port 3 pins
P5DDR—Port 5 Data Direction Register
H'FEB4
Port 5
Bit
:
7
6
5
4
3
2
1
0
—
—
—
— P53DDR P52DDR P51DDR P50DDR
Initial value : _{Undefined Undefined Undefined Undefined 0}
0
0
0
Read/Write : _—
—
—
—
W
W
W
W
Specify input or output for individual port 5 pins
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