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HD6432351 Datasheet, PDF (69/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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Table 2-3 Instructions Classified by Function (cont)
Type
Instruction
System control TRAPA
instructions RTE
SLEEP
LDC
Size*
â
â
â
B/W
STC
B/W
ANDC
B
ORC
B
XORC
B
NOP
â
Note: * Size refers to the operand size.
B: Byte
W: Word
Function
Starts trap-instruction exception handling.
Returns from an exception-handling routine.
Causes a transition to a power-down state.
(EAs) â CCR, (EAs) â EXR
Moves the source operand contents or immediate data
to CCR or EXR. Although CCR and EXR are 8-bit
registers, word-size transfers are performed between
them and memory. The upper 8 bits are valid.
CCR â (EAd), EXR â (EAd)
Transfers CCR or EXR contents to a general register or
memory. Although CCR and EXR are 8-bit registers,
word-size transfers are performed between them and
memory. The upper 8 bits are valid.
CCR ⧠#IMM â CCR, EXR ⧠#IMM â EXR
Logically ANDs the CCR or EXR contents with
immediate data.
CCR ⨠#IMM â CCR, EXR ⨠#IMM â EXR
Logically ORs the CCR or EXR contents with immediate
data.
CCR â #IMM â CCR, EXR â #IMM â EXR
Logically exclusive-ORs the CCR or EXR contents with
immediate data.
PC + 2 â PC
Only increments the program counter.
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