HD6432351 Datasheet, PDF (679/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

19.2 Register Descriptions
19.2.1 System Clock Control Register (SCKCR)
Bit
:
7
6
5
4
3
2
1
0
PSTOP —
—
—
—
SCK2 SCK1 SCK0
Initial value:
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
—
—
—
R/W R/W R/W
SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-
speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—ø Clock Output Disable (PSTOP): Controls ø output.
Bit 7
PSTOP
0
1
Normal Operation
ø output (initial value)
Fixed high
Description
Sleep Mode
Software
Standby Mode
ø output
Fixed high
Fixed high
Fixed high
Hardware
Standby Mode
High impedance
High impedance
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.
Bits 5 to 3—Reserved: Read-only bits, always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus
master.
Bit 2
SCK2
0
1
Bit 1
SCK1
0
1
0
1
Bit 0
SCK0
0
1
0
1
0
1
—
Description
Bus master is in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
(Initial value)
659