HD6432351 Datasheet, PDF (223/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor
(activation source). There are some differences in activation sources for channel A and for channel
B.
Channel A
Bit 3
DTF3
0
1
Bit 2
DTF2
0
1
0
1
Bit 1
DTF1
0
1
0
1
0
1
0
1
Bit 0
DTF0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
—
(Initial value)
Activated by A/D converter conversion end interrupt
—
—
Activated by SCI channel 0 transmission complete interrupt
Activated by SCI channel 0 reception complete interrupt
Activated by SCI channel 1 transmission complete interrupt
Activated by SCI channel 1 reception complete interrupt
Activated by TPU channel 0 compare match/input capture
A interrupt
Activated by TPU channel 1 compare match/input capture
A interrupt
Activated by TPU channel 2 compare match/input capture
A interrupt
Activated by TPU channel 3 compare match/input capture
A interrupt
Activated by TPU channel 4 compare match/input capture
A interrupt
Activated by TPU channel 5 compare match/input capture
A interrupt
—
—
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