HD6432351 Datasheet, PDF (227/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 1B data transfer
factor setting.
Bit 11
DTA1B
0
1
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 1A data transfer
factor setting.
Bit 10
DTA1A
0
1
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 0B data transfer
factor setting.
Bit 9
DTA0B
0
1
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 0A data transfer
factor setting.
Bit 8
DTA0A
0
1
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
Clearing of selected internal interrupt source at time of DMA transfer is enabled
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