HD6432351 Datasheet, PDF (292/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7-13.
During burst transfer, or when one block is being transferred in block transfer, the channel will not
be changed until the end of the transfer.
Figure 7-35 shows a transfer example in which transfer requests are issued simultaneously for
channels 0A, 0B, and 1.
DMA read DMA write
DMA read DMA write
DMA
DMA read DMA write read
ø
Address bus
RD
HWR
LWR
DMA control Idle Read Write
Idle Read Write
Idle Read Write
Read
Channel 0A Request clear
Channel 0B
Channel 1
Bus
release
Request Selection Request clear
hold
Request
hold
Non-
selection
Request _Selection ^{Request clear}
hold
Channel 0A
transfer
Bus
release
Channel 0B
transfer
Bus
release
Channel 1 transfer
Figure 7-35 Example of Multi-Channel Transfer
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