HD6432351 Datasheet, PDF (36/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 1-3 Pin Functions (cont)
Pin No.
Type
Symbol TFP-120 FP-128 I/O Name and Function
Bus control
WAIT
86
94
Input Wait: Requests insertion of a wait
state in the bus cycle when
accessing external 3-state address
space.
LCAS
86
94
Output Lower column address strobe: The 2-
CAS type DRAM lower column
address strobe signal
DMA controller DREQ1, 62, 60
(DMAC)
DREQ0
70, 66
Input DMA request 1 and 0: These pins
request DMAC activation.
TEND1,
TEND0
63, 61
71, 69
Output DMA transfer end 1 and 0: These
pins indicate the end of DMAC data
transfer.
DACK1,
DACK0
111, 112 121, 122 Output DMA transfer acknowledge 1 and 0:
These are the DMAC single address
transfer acknowledge pins.
16-bit timer-
pulse unit
(TPU)
TCLKD to 105, 107, 115, 117, Input Clock input D to A: These pins input
TCLKA 109, 110 119, 120
an external clock.
TIOCA0, 112 to 122 to I/O
TIOCB0, 109
119
TIOCC0,
TIOCD0
Input capture/ output compare match
A0 to D0: The TGR0A to TGR0D
input capture input or output compare
output, or PWM output pins.
TIOCA1, 108, 107 118, 117 I/O
TIOCB1
Input capture/ output compare match
A1 and B1: The TGR1A and TGR1B
input capture input or output compare
output, or PWM output pins.
TIOCA2, 106, 105 116, 115 I/O
TIOCB2
Input capture/ output compare match
A2 and B2: The TGR2A and TGR2B
input capture input or output compare
output, or PWM output pins.
TIOCA3,
TIOCB3,
TIOCC3,
TIOCD3
71 to 68 79 to 76 I/O
Input capture/ output compare match
A3 to D3: The TGR3A to TGR3D
input capture input or output compare
output, or PWM output pins.
16