HD6432351 Datasheet, PDF (840/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

IPRA — Interrupt Priority Register A
IPRB — Interrupt Priority Register B
IPRC — Interrupt Priority Register C
IPRD — Interrupt Priority Register D
IPRE — Interrupt Priority Register E
IPRF — Interrupt Priority Register F
IPRG — Interrupt Priority Register G
IPRH — Interrupt Priority Register H
IPRI — Interrupt Priority Register I
IPRJ — Interrupt Priority Register J
IPRK — Interrupt Priority Register K
H'FEC4
H'FEC5
H'FEC6
H'FEC7
H'FEC8
H'FEC9
H'FECA
H'FECB
H'FECC
H'FECD
H'FECE
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Bit
:
7
6
5
4
3
2
1
0
—
IPR6 IPR5 IPR4
—
IPR2 IPR1 IPR0
Initial value :
0
1
1
1
0
1
1
1
Read/Write :
—
R/W R/W R/W
—
R/W
R/W
R/W
Set priority (levels 7 to 0) for interrupt sources
Correspondence between Interrupt Sources and IPR Settings
Register
6 to 4
IPRA IRQ0
IPRB IRQ2
IRQ3
IPRC IRQ6
IRQ7
IPRD WDT
IPRE —*
IPRF TPU channel 0
IPRG TPU channel 2
IPRH TPU channel 4
IPRI —*
IPRJ DMAC
IPRK SCI channel 1
Bits
IRQ1
IRQ4
IRQ5
DTC
2 to 0
Refresh timer
A/D converter
TPU channel 1
TPU channel 3
TPU channel 5
—*
SCI channel 0
—*
Note: * Reserved bits. These bits cannot be modified and are
always read as 1.
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