HD6432351 Datasheet, PDF (785/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

A.5 Bus States During Instruction Execution
Table A-6 indicates the types of cycles that occur during instruction execution by the CPU. See
table A-4 for the number of states per cycle.
How to Read the Table:
Order of execution
Instruction
1
2
3
4
5
6
7
8
JMP@aa:24
Internal operation
R:W 2nd _{1 state}
R:W EA
End of instruction
Read effective address (word-size read)
No read or write
Read 2nd word of current instruction
(word-size read)
Legend
R:B
R:W
W:B
W:W
:M
2nd
3rd
4th
5th
NEXT
EA
VEC
Byte-size read
Word-size read
Byte-size write
Word-size write
Transfer of the bus is not performed immediately after this cycle
Address of 2nd word (3rd and 4th bytes)
Address of 3rd word (5th and 6th bytes)
Address of 4th word (7th and 8th bytes)
Address of 5th word (9th and 10th bytes)
Address of next instruction
Effective address
Vector address
765