HD6432351 Datasheet, PDF (629/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

14.3.6 Data Transfer Operations
Initialization: Before transmitting and receiving data, initialize the SCI as described below.
Initialization is also necessary when switching from transmit mode to receive mode, or vice versa.
[1] Clear the TE and RE bits in SCR to 0.
[2] Clear the error flags ERS, PER, and ORER in SSR to 0.
[3] Set the O/E bit and CKS1 and CKS0 bits in SMR. Clear the C/A, CHR, and MP bits to 0, and
set the STOP and PE bits to 1.
[4] Set the SMIF, SDIR, and SINV bits in SCMR.
When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins,
and are placed in the high-impedance state.
[5] Set the value corresponding to the bit rate in BRR.
[6] Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE and CKE1 bits to 0.
If the CKE0 bit is set to 1, the clock is output from the SCK pin.
[7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE
bit and RE bit at the same time, except for self-diagnosis.
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