HD6432351 Datasheet, PDF (523/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

11.2.9 Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
When the MSTP11 bit in MSTPCR is set to 1, PPG operation stops at the end of the bus cycle and
a transition is made to module stop mode. Registers cannot be read or written to in module stop
mode. For details, see section 20.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 11—Module Stop (MSTP11): Specifies the PPG module stop mode.
Bit 11
MSTP11
0
1
Description
PPG module stop mode cleared
PPG module stop mode set
(Initial value)
503