HD6432351 Datasheet, PDF (937/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

C.3 Port 3 Block Diagram
*1
P3_n
*2
Reset
R
Q
D
P3nDDR
C
WDDR3
Reset
R
Q
D
P3nDR
C
WDR3
Reset
R
Q
D
P3nODR
C
WODR3
RODR3
RDR3
SCI module
Serial transmit enable
Serial transmit data
RPOR3
Legend
WDDR3 : Write to P3DDR
WDR3 : Write to P3DR
WODR3 : Write to P3ODR
RDR3 : Read P3DR
RPOR3 : Read port 3
RODR3 : Read P3ODR
n = 0 or 1
Notes: 1. Output enable signal
2. Open drain control signal
Figure C-3 (a) Port 3 Block Diagram (Pins P3₀ and P3₁)
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